Current software-based packet classification algorithms exhibit relatively poor performance, prompting many researchers to\r\nconcentrate on novel frameworks and architectures that employ both hardware and software components.ThePacket Classification\r\nwith Incremental Update (PCIU) algorithm, Ahmed et al. (2010), is a novel and efficient packet classification algorithm with a\r\nunique incremental update capability that demonstrated excellent results and was shown to be scalable for many different tasks and\r\nclients. While a pure software implementation can generate powerful results on a server machine, an embedded solution may be\r\nmore desirable for some applications and clients. Embedded, specialized hardware accelerator based solutions are typically much\r\nmore efficient in speed, cost, and size than solutions that are implemented on general-purpose processor systems. This paper seeks\r\nto explore the design space of translating the PCIU algorithm into hardware by utilizing several optimization techniques, ranging\r\nfrom fine grain to coarse grain and parallel coarse grain approaches.The paper presents a detailed implementation of a hardware\r\naccelerator of the PCIU based on an Electronic System Level (ESL) approach. Results obtained indicate that the hardware accelerator\r\nachieves on average 27x speedup over a state-of-the-art Xeon processor.
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